Theory & Background

KiCad schematic: start with block diagram — identify all functional blocks and their connections. Power symbols: use PWR_FLAG on all power rails (prevents ERC false errors). Decoupling capacitors: every IC power pin gets 100nF (0402) within 1mm, bulk 10µF per power domain. Component hierarchy: group into hierarchical sheets for complex designs (power, MCU, peripheral). Net labels: use named labels for long-range connections instead of wires (cleaner schematic). ERC (Electrical Rules Check): fix all errors before layout. Export netlist for PCB import.

Components & Requirements

10 components required for this project.

#	Component	Purpose	Qty
1	KiCad 7 (free EDA software)	Schematic capture and PCB layout	x1
2	JLCPCB or PCBWay fabrication order	PCB manufacturing (4-layer)	x1
3	SMT stencil (laser-cut stainless, 0.12mm)	Solder paste application	x1
4	Solder paste (Sn63/Pb37 or SAC305 lead-free)	SMT solder medium	x1
5	Hotplate / reflow oven / heat gun	Soldering	x1
6	SMT components (0402, QFN, SOT-23 packages)	Surface mount components	x1
7	USB microscope or loupe (10×)	Solder joint inspection	x1
8	Flux (RMA type, no-clean)	Soldering aid and oxide removal	x1
9	Multimeter + LCR meter	Post-assembly testing	x1
10	JTAG/SWD programmer	MCU firmware flashing	x1

Step-by-Step Implementation

Follow these 5 steps carefully.

1

Schematic Design Best Practices

KiCad schematic: start with block diagram — identify all functional blocks and their connections. Power symbols: use PWR_FLAG on all power rails (prevents ERC false errors). Decoupling capacitors: every IC power pin gets 100nF (0402) within 1mm, bulk 10µF per power domain. Component hierarchy: group into hierarchical sheets for complex designs (power, MCU, peripheral). Net labels: use named labels for long-range connections instead of wires (cleaner schematic). ERC (Electrical Rules Check): fix all errors before layout. Export netlist for PCB import.

2

4-Layer PCB Stack-up

4-layer stack: L1 (Signal/Components), L2 (Ground plane — solid copper, no splits), L3 (Power plane — different voltages as copper fills), L4 (Signal). Benefits: L2 ground plane provides return path for all L1 signals, controlled impedance, EMI shielding, power distribution. Via: drill through all 4 layers (through-hole via) for signals. Blind/buried vias: for HDI designs (expensive — avoid for prototype). Design rules: JLCPCB 4-layer minimum: 0.1mm trace, 0.1mm space, 0.3mm drill. Impedance-controlled trace width for 50Ω: L1/L4 trace over L2/L3 ground.

3

Component Placement Strategy

Placement flow: connector first (fixed by mechanical constraints), MCU/main IC second (by signal flow), then supporting components. High-speed signals (USB, SPI, oscillator): short traces, away from noisy circuits. Decoupling caps: immediately adjacent to power pins. Crystal: directly on MCU pins, no vias between. Heat-generating components: near board edge for airflow, not under other heat-sensitive parts. Mechanical clearance: check DRC for component clearance violations. Silkscreen: label all connectors, test points, polarity marks.

4

Routing and Signal Integrity

Routing priorities: power and ground first (fill pours), then high-speed signals (USB D+/D- differential pair — route together, matched length ±5 mil), then remaining signals. Differential pairs: route together with equal length ±0.1mm, constant spacing (set in KiCad Interactive Router). 90° corners: avoid in RF/high-speed (use 45° or curves). Copper fills: pour ground on L1 and L4, connect to L2 ground with stitching vias every 5–10mm. Keep-out zones: no copper under antenna (if present), no copper under crystal resonator.

5

SMT Assembly with Stencil

Stencil printing: tape PCB to flat surface, align stencil (apertures match pads), squeegee solder paste at 45° — one smooth pass. Check: every pad has correct amount of paste (no bridges, no voids). Component placement: tweezers or pick-and-place. Place smallest components first (0402), then ICs, then connectors. QFN packages: paste only on pads (not under thermal pad — causes floating). Reflow profile: preheat 150°C (2 minutes), soak 180°C (1 minute), reflow peak 230°C for SAC305 (20 seconds), cooling. Inspect under 10× microscope: check for bridges, tombstoning, missing components.

Code & Implementation

Core code for pcb_stackup_calc.py:

pcb_stackup_calc.py
  Python

# PCB Impedance Calculator # Calculate trace width for 50Ω microstrip (IPC-2141A formula)  import math  def microstrip_impedance(w_mm, h_mm, t_mm=0.035, er=4.5):     """     Calculate microstrip characteristic impedance.     w: trace width (mm)     h: dielectric thickness (mm)     t: copper thickness (mm, 1oz = 0.035mm)     er: relative permittivity (FR4 ≈ 4.5 at 1 GHz)     """     w_eff = w_mm + (t_mm / math.pi) * math.log(4 * math.e / math.sqrt((t_mm / h_mm)**2 + (t_mm / (w_mm * math.pi))**2))          if w_eff / h_mm < 1:         Z0 = (60 / math.sqrt(er)) * math.log(8 * h_mm / w_eff + w_eff / (4 * h_mm))     else:         Z0 = (120 * math.pi / math.sqrt(er)) / (w_eff / h_mm + 1.393 + 0.667 * math.log(w_eff / h_mm + 1.444))     return Z0  def find_50ohm_width(h_mm, t_mm=0.035, er=4.5, target=50, tol=0.1):     """Binary search for trace width giving target impedance."""     lo, hi = 0.05, 5.0     for _ in range(50):         mid = (lo + hi) / 2         z = microstrip_impedance(mid, h_mm, t_mm, er)         if abs(z - target) < tol:             return mid, z         if z > target:             lo = mid         else:             hi = mid     return mid, z  # JLCPCB 4-layer standard stackup print("=== PCB Impedance Calculator ===") print("JLCPCB JLC04161H-3313 4-layer stackup\\n")  layers = [     ("L1 (signal) to L2 (GND)", 0.1, 4.05),   # 100µm core     ("L2 (GND) to L3 (PWR)", 1.2, 4.05),      # 1.2mm core     ("L3 (PWR) to L4 (signal)", 0.1, 4.05),   # 100µm core ]  for desc, h, er in layers:     w, z = find_50ohm_width(h, er=er)     print(f"{desc}: {w:.3f} mm wide → {z:.1f} Ω (50Ω target)")      print("\\nVerification:") w_test = 0.200  # Typical 50Ω trace width for L1/L4 to L2/L3 print(f"0.200mm trace on 0.1mm dielectric: Z0 = {microstrip_impedance(w_test, 0.1):.1f} Ω")

Testing & Troubleshooting

Test PCB Design and SMT Assembly by verifying each subsystem individually before full integration.

!

Troubleshooting Tips

Verify power voltages, check ground connections, use serial monitor for debug.

Real-World Applications

*MCU-based sensor interface board

*Motor driver PCB design

*RF frontend board design

*Power management module design

*Prototype for product development

*Educational electronics experimentation platform

*Custom Arduino shield design

*Measurement and test instrument PCB

Extensions & Next Steps

Design a high-density BGA PCB with via-in-pad technology
Implement DDR3/4 memory layout with length matching
Design an RF-shielded section with Faraday cage via wall
Build an automated optical inspection (AOI) test setup for PCBs
Create a PCB badge with LED animations for maker events

Interactive Playground

Coming Soon

An interactive simulator will be available here — simulate circuits and run code in-browser without hardware.

Frequently Asked Questions

What causes PCB trace impedance to matter and when can I ignore it?

Trace impedance mismatches cause signal reflections — portion of signal bounces back from load, creating ringing and potentially corrupting data. Rule of thumb: consider impedance when trace length > λ/10 of the signal's highest frequency component. For a 100 MHz signal (λ = 3m): λ/10 = 30cm → traces > 30cm need controlled impedance. Most digital traces in small boards are short enough to ignore. Exceptions: always control impedance for USB (90Ω differential), HDMI/DisplayPort (100Ω diff), RF (50Ω), Ethernet (100Ω diff), DDR memory (50Ω single-ended, 100Ω differential). Unterminated reflections cause EMC compliance failures.

Introduction